DocumentCode :
318845
Title :
Design of C-testable multipliers based on the modified Booth Algorithm
Author :
Boateng, Kwame Osei ; Takabashi, H. ; Takamatsu, Yuzo
Author_Institution :
Fac. of Eng., Ehime Univ., Matsuyama, Japan
fYear :
1997
fDate :
17-19 Nov 1997
Firstpage :
42
Lastpage :
47
Abstract :
In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns
Keywords :
VLSI; design for testability; logic arrays; logic design; multiplying circuits; VLSI; c-testability; c-testable multipliers; cell fault model; logic array; logic design; modified Booth algorithm; single stuck fault model; test sequence; Algorithm design and analysis; Circuit faults; Circuit testing; Computer science; Design engineering; Encoding; Hardware; Switches; Test pattern generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
ISSN :
1081-7735
Print_ISBN :
0-8186-8209-4
Type :
conf
DOI :
10.1109/ATS.1997.643914
Filename :
643914
Link To Document :
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