Parameter extraction and calorimetric validation for a silicon carbide JFET PSpice model

This paper focuses on the PSpice model of SiC-JFET element inside a SiCED cascode device. The device model parameters are extracted from the I–V and C-V characterization curves. In order to validate the model, an inductive test rig circuit is designed and tested. The switching loss is estimated both using oscilloscope and calorimeter. These results are found to be in good agreement with the simulated results.