Title :
Accelerated test points selection method for scan-based BIST
Author :
Nakao, Michinobu ; Hatayama, Kazumi ; Higashi, Isao
Author_Institution :
Res. Lab., Hitachi Ltd., Ibaraki, Japan
Abstract :
This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates)
Keywords :
built-in self test; economics; integrated circuit manufacture; integrated circuit testing; integrated logic circuits; logic testing; minimisation; cost reduction; large scale circuits; plural test points; random pattern testability; scan-based BIST; test points selection; Built-in self-test; Circuit faults; Circuit testing; Costs; Laboratories; Large-scale systems; Life estimation; Logic circuits; Logic testing; Minimization methods;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643983
