Title :
A low power, high SFDR, ROM-less direct digital frequency synthesizer
Author :
Jafari, H. ; Ayatollahi, A. ; Mirzakuchaki, S.
Author_Institution :
Dept. of Electr. Eng., Iran Univ. of Sci. & Tech., Tehran, Iran
Abstract :
This paper describes the design of a ROM-less direct digital frequency synthesizer. The spurious free dynamic range (SFDR) of the proposed DDFS system is -91.51dBc. A DDFS IC has been designed in HP 0.5μm standard N-Well CMOS process technology, and that´s layout has 2.489mm2 area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz.
Keywords :
CMOS integrated circuits; circuit layout; direct digital synthesis; low-power electronics; 0.5 micron; 100 MHz; 3.3 V; 32 bit; 60 mW; IC design; circuit layout; direct digital frequency synthesizer; frequency control word; spurious free dynamic range; standard N-well CMOS process technology; CMOS integrated circuits; Dynamic range; Energy consumption; Frequency control; Frequency synthesizers; Function approximation; Genetic algorithms; Polynomials; Read only memory; Taylor series; Direct digital frequency synthesizer (DDFS); ROM-Less; frequency synthesizer;
Conference_Titel :
Microelectronics, 2005. ICM 2005. The 17th International Conference on
Print_ISBN :
0-7803-9262-0
DOI :
10.1109/ICM.2005.1590035
