Testing of resistive opens in CMOS latches and flip-flops

Author

Champac, Victor H. ; Zenteno, Antonio ; García, José L.

Author_Institution

Dept. of Electron. Eng., National Inst. for Astrophys., Puebla, Mexico

fYear

2005

fDate

22-25 May 2005

Firstpage

34

Lastpage

40

Abstract

Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high resistive opens in gates. These defects depend on initial conditions prior to the application of the test vectors. Test conditions influencing the detectability of opens in scan path chains are also analyzed. Some sequences of 1´s and 0´s may fail for detecting opens in gates. Conditions for the input sequences for scan path chains are stated. The dependence of the detectability of opens on the duty cycle is also investigated. Experimental results showing the dependence of the behavior of open gates with the initial conditions are shown.

Keywords

CMOS logic circuits; flip-flops; logic testing; CMOS flip-flops; CMOS latches; CMOS logic circuits; CMOS memory elements; input sequences; logic gates; logic testing; resistive opens testing; scan path chains; Astrophysics; Circuit faults; Circuit testing; Conducting materials; Delay; Design for testability; Fault detection; Flip-flops; Latches; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2005. European

Print_ISBN

0-7695-2341-2

Type

conf

DOI

10.1109/ETS.2005.41

Filename

1430006