SystemC space exploration of behavioral synthesis options on area, performance and power consumption

SystemC based design of system on chip is gaining popularity and designers are increasingly faced with the need to synthesize at the highest level of abstraction. Although RTL level SystemC design synthesis is common behavioral level SystemC design synthesis is still not widely accepted. The objective of this paper is to present methodology for behavioral synthesis of SystemC design. It gives the possibility to detect the best synthesis results on area, performance and power consumption estimation through an automatic exploration of synthesis results. This framework allows SystemC level design space exploration of SoC.