DocumentCode :
3189081
Title :
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization
Author :
Dilillo, Luigi ; Girard, Patrick ; Pravossoudovitch, Serge ; Virazel, Arnaud ; Hage-Hassan, Magali Bastian
Author_Institution :
LIRMM, Univ. de Montpellier, France
fYear :
2005
fDate :
22-25 May 2005
Firstpage :
116
Lastpage :
121
Abstract :
In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.
Keywords :
SRAM chips; fault simulation; integrated circuit testing; SRAM memories; pre-charge circuits; resistive defect detection; resistive-open defect; un-restored read faults; un-restored write faults; write/read operation; Circuit analysis; Circuit testing; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2005. European
Print_ISBN :
0-7695-2341-2
Type :
conf
DOI :
10.1109/ETS.2005.33
Filename :
1430018
Link To Document :
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