Title :
Optimization of UHF voltage multiplier circuit for RFID application
Author :
Bergeret, Emmanuel ; Pannier, Philippe ; Gaubert, Jean
Author_Institution :
L2MP-Polytech, IMT Technople de Chateai Gombert, Marseille, France
Abstract :
This paper presents study and optimization of diode multiplier including antenna matching problems. Results on a voltage multiplier designed in 0.18μm CMOS process have been shown. It can power a chip at a distance of 10 m with an efficiency of 30%. In this paper, we present a simple analytical model of the complete tag: antenna and chip. This model allows us to explain many results on crucial points of voltage multiplier design. We also present limitations of this kind of structure.
Keywords :
CMOS integrated circuits; UHF integrated circuits; radiofrequency identification; voltage multipliers; 0.18 micron; 10 m; 30 percent; CMOS process; RFID application; UHF voltage multiplier circuit; antenna matching; diode multiplier; voltage multiplier design; Analytical models; CMOS process; Diodes; Impedance; Power supplies; Radio frequency; Radiofrequency identification; Transponders; UHF circuits; Voltage;
Conference_Titel :
Microelectronics, 2005. ICM 2005. The 17th International Conference on
Print_ISBN :
0-7803-9262-0
DOI :
10.1109/ICM.2005.1590062
