NoC Design of a Video Encoder in a Multiprocessor System on Chip Solution

Future multiprocessor system-on-a-chip (MPSoC) will need high performance and low power requirements due to user demand and limited battery life. In this paper, we take advantage of the architecture flexibility allowed by Network-on-Chip (NoC) to build a parameterizable MPEG Compressor. MPEG compressor System has been developed in synthetizable behavioural SystemC, as a flexible system divided in different tiles. Each tile can be configured as a functional block with different performance parameters in terms of power/speed/area. NoC design implements a 2D mesh with a parameterizable router implemented in high level TLM SystemC. A QoS module takes decisions on packet routing depending on macro-block encoded data (corresponding to I, P and B frames) in real time in terms of power or performance requirements.