Title :
Low level image processing operators on FPGA: implementation examples and performance evaluation
Author :
De Barros, Marcelo Alves ; Akil, Mohamed
Author_Institution :
Lab. IAAI, Group ESIEE, Noisy le Grand, France
Abstract :
This work deals with evaluation of hardware implementations of image processing algorithms for real time applications, using SRAM based field-programmable gate arrays. We discuss a generic architectural model adapted to this domain and to the technology characteristics. A method to evaluate the area costs and timing performances of architectures implemented on such a model is presented. A feasibility study of a pre-processing chain in an image-recognition system is presented
Keywords :
image processing equipment; FPGA; SRAM based field-programmable gate arrays; generic architectural model; image-recognition system; low-level image processing operators; performance evaluation; pre-processing chain; Circuit testing; Computer architecture; Costs; Field programmable gate arrays; Hardware; Image processing; Logic testing; Performance evaluation; System testing; Timing;
Conference_Titel :
Pattern Recognition, 1994. Vol. 3 - Conference C: Signal Processing, Proceedings of the 12th IAPR International Conference on
Conference_Location :
Jerusalem
Print_ISBN :
0-8186-6275-1
DOI :
10.1109/ICPR.1994.577173
