Title :
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire
Author :
Lee, Tai-Cheng ; Razavi, Behzad
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A discrete-time mixed-signal linear equalizer designed for the analog front end of Gigabit Ethernet receivers performs cable equalization while relaxing the A/D converter complexity. Based on a coefficient-rotating FIR filter architecture, the circuit incorporates 8 taps that are adapted to the cable characteristics by means of an LMS algorithm. A distributed array of interleaved sampling circuits and a linear low-voltage multiplier topology allow both high speed and low power dissipation. Fabricated in a 0.25-μm digital CMOS technology, the equalizer operates at 125 MHz while dissipating 75 mW from a 2.5-V power supply
Keywords :
CMOS integrated circuits; FIR filters; equalisers; high-speed integrated circuits; least mean squares methods; local area networks; mixed analogue-digital integrated circuits; twisted pair cables; 0.25 micron; 125 MHz; 2.5 V; 75 mW; A/D converter complexity; ADC complexity relaxation; ASIC; CMOS mixed-signal equalizer; Gigabit Ethernet; LMS algorithm; analog front end; cable equalization; coefficient-rotating FIR filter architecture; copper wire; digital CMOS technology; discrete-time linear equalizer; distributed array; interleaved sampling circuits; linear LV multiplier topology; low-voltage multiplier topology; CMOS technology; Circuit topology; Copper; Equalizers; Ethernet networks; Finite impulse response filter; Least squares approximation; Power dissipation; Signal processing; Wire;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929740
