A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology

Author

Huss, Scott ; Mullen, Mark ; Gray, C. Thomas ; Smith, Randall ; Summers, Mark ; Shafer, Jeff ; Heron, Pat ; Sawinska, Tim ; Medero, Joe

Author_Institution

Analog & Mixed Signal Design Center, Tality Corp., Cary, NC, USA

fYear

2001

fDate

2001

Firstpage

135

Lastpage

138

Abstract

This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 μm single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm² and consumes 350 mW of power

Keywords

CMOS digital integrated circuits; data communication equipment; digital communication; digital signal processing chips; local area networks; synchronisation; transceivers; 0.18 micron; 1.8 V; 10BaseT/100BaseTX Ethernet transceiver; 150 m; 350 mW; DSP architecture; DSP-based Ethernet transceiver; Ethernet physical layer interface; IEEE 802.3 compliant transceiver; integrated transceiver; single-poly 5-level metal CMOS technology; timing recovery; CMOS technology; Dielectric losses; Digital signal processing; Ethernet networks; Finite impulse response filter; Integrated circuit noise; Robustness; Transceivers; Transformers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929741

Filename

929741