Title :
Design techniques for very low power ADCs
Author :
Taft, Robert C. ; Tursi, Maria Rosaria ; Glenny, Andrew
Author_Institution :
Nat. Semiconductor East Coast Labs., Furstenfeldbruck, Germany
Abstract :
The three low-power ADC techniques of interleaving-by-4 with an amplifier reset and master sampling clock, using self-regulating CMOS push-pull amplifiers, and a hybrid comparator are described. They are demonstrated in an 8-bit 100 MSPS ADC which achieves +/- 0.25 LSB DNL and 7.5 effective bits with very low power, 54 mW at 2.7 V supply. The same 8-bit ADC, if optimized for 200 MSPS operation at 2.7 V, obtains a DNL below 0.4 LSB, and 7.3 (7.1) effective bits for a 10 MHz (100 MHz) input while consuming just 182 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; low-power electronics; 10 MHz; 100 MHz; 182 mW; 2.7 V; 54 mW; 8 bit; A/D convertors; amplifier reset; design techniques; hybrid comparator; interleaving-by-4 scheme; low power ADCs; low-power ADC techniques; master sampling clock; self-regulating CMOS push-pull amplifiers; subranging architecture; CMOS technology; Circuits; Clocks; Interleaved codes; Inverters; Power amplifiers; Sampling methods; Switches; Timing; Voltage;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929742
