A low power, 10-bit CMOS D/A converter for high speed applications

Author

Borremans, M. ; Van Den Bosch, A. ; Steynaert, M. ; Sansen, W.

Author_Institution

Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium

fYear

2001

fDate

2001

Firstpage

157

Lastpage

160

Abstract

In this paper, the realization of a fully binary 10-bit current steering CMOS DAC is presented. Both the measured INL and DNL are smaller than 0.2 LSB. Better than 60 dB SFDR is achieved for all output signals up to a 30 MS/s Nyquist frequency. For a 1 MHz signal, the chip achieves better than 60 dB SFDR for all update rates up to 800 MS/s. The presented DAC core occupies 0.23 mm². The digital power consumption is only 1 mW for a 30 MS/s Nyquist operation. Based on a fundamental theoretical INL- and DNL-yield analysis, the presented design explores the limits towards the binary and the low-power edges of the design space

Keywords

CMOS integrated circuits; digital-analogue conversion; high-speed integrated circuits; low-power electronics; 1 mW; 10 bit; CMOS D/A converter; DNL-yield analysis; INL-yield analysis; Nyquist operation; current steering CMOS DAC; fully binary CMOS DAC; high speed applications; low power CMOS DAC; Energy consumption; Gaussian distribution; Matrix converters; Prototypes; Semiconductor device measurement; Silicon; Switches; Switching converters; Synchronization; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929746

Filename

929746