Area efficiency PLL design using capacitance multiplication based on self-biased architecture

An ring-oscillator based, area efficiency self-biased clock generator phase-locked loop (PLL) design is presented. With the already existing dual-loop and summing amplifier in the self-biased architecture, a capacitance multiplication method has been used to greatly save the area of the PLL with nearly no other impact on the total performance. Power supply rejection issue is considered, and a zero-offset, glitch-free charge pump is presented. Fabricated in 0.18-μm CMOS process, the PLL could operate from 50 to 600MHz, the measured phase noise is -102dBc@1MHz when output at 240MHz, the core die area is only 0.078mm².