A fast analytical technique for estimating the bounds of on-chip clock wire inductance

Accurate integrity assessment of on-chip clock lines is difficult without any a priori knowledge about their inductance at an early stage in the clock design process. This paper introduces an efficient approach to estimate the bounds of on-chip clock wire inductance at the very beginning of the design stages. With this information, more accurate waveforms along the clock distribution networks can be obtained thus greatly reducing the overall length of design cycles