Title :
A fast analytical technique for estimating the bounds of on-chip clock wire inductance
Author :
Lu, Yi-Chang ; Banerjee, Kaustav ; Celik, Mustafa ; Dutton, Robert W.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Accurate integrity assessment of on-chip clock lines is difficult without any a priori knowledge about their inductance at an early stage in the clock design process. This paper introduces an efficient approach to estimate the bounds of on-chip clock wire inductance at the very beginning of the design stages. With this information, more accurate waveforms along the clock distribution networks can be obtained thus greatly reducing the overall length of design cycles
Keywords :
VLSI; delay estimation; digital integrated circuits; inductance; integrated circuit interconnections; integrated circuit modelling; timing; transient response; bounds estimation; clock design process; clock distribution networks; fast analytical technique; impulse response; integrity assessment; onchip clock wire inductance; Clocks; Delay estimation; Inductance; Pins; Process design; Routing; Skin; System-on-a-chip; Very large scale integration; Wire;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929764
