Title :
Effect of RTL coding style on testability
Author :
Huang, Yu ; Tsai, Chien-Chung ; Mukherhee, N. ; Cheng, Wu-Tung ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
This paper illustrates the effect of functional Register Transfer-Level (RTL) coding styles on the testability of synthesized gate-level circuits. Thus, the advantage of having an RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testability reduces the total silicon area of the gate-level circuit as well. Experimental results presented in this paper demonstrate the benefits of having a proposed RTL code analyzer
Keywords :
circuit CAD; design for testability; integrated circuit design; integrated circuit testing; logic CAD; logic testing; redundancy; DFT; RTL code analyzer; RTL coding style; register transfer level coding; synthesized gate-level circuits; testability; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Degradation; Logic design; Logic testing; Redundancy; Signal generators; Silicon;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929767
