A 1.0 GS/s 7bit Pipelined-Folding-Interpolating ADC with 6.0 ENOB at nyquist frequency

Author

Wang, Mingshuo ; Lin, Li ; Xia, Jiefeng ; Ye, Fan ; Li, Ning ; Ren, Junyan

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

177

Lastpage

180

Abstract

A single-channel 1.0 GS/s 7bit Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. A fine and coarse joint encoding method is proposed to simplify the analog preprocessing of the coarse sub-ADC and to save power and chip area. Double-diode bootstrapped interstage switch is adopted to improve the overall efficiency of speed. The ADC implemented in 0.13-μm CMOS achieves SNDR of 37.89 dB and SFDR of 45.89 dB for 498MHz input frequency located at 1.0GS/s. The power consumption is 110mW with sampling rate of 1.0GS/s and supply voltage of 1.5/2.5 V.

Keywords

analogue-digital conversion; bootstrap circuits; encoding; interpolation; low-power electronics; Nyquist frequency; analog preprocessing; analog-to-digital converter; coarse sub-ADC; double-diode bootstrapped interstage switch; frequency 498 MHz; joint encoding method; pipelined-folding-interpolating ADC; power 110 mW; size 0.13 mum; voltage 1.5 V; voltage 2.5 V; word length 7 bit; Arrays; CMOS integrated circuits; Capacitors; Encoding; Interpolation; Joints; Switches; ADC and CMOS; Folding and Interpolating;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology (RFIT), 2011 IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4577-0517-5

Type

conf

DOI

10.1109/RFIT.2011.6141770

Filename

6141770