• DocumentCode
    3190278
  • Title

    Analysis and simulation of a 2nd order ΔΣ modulator with single-comparator multi-bit quantizer

  • Author

    Liu, Liyuan ; Li, DongMei ; Ye, Yafei ; Wang, ZhiHua

  • Author_Institution
    Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
  • fYear
    2011
  • fDate
    Nov. 30 2011-Dec. 2 2011
  • Firstpage
    189
  • Lastpage
    192
  • Abstract
    A 2nd order ΔΣ modulator is presented. The feed forward topology with multi-bit quantizer is adopted. The digital summing is used. Single comparator successive approximation quantizer is proposed. Non-ideal effects of the quantizer such as comparator offset, components mismatch are modeled and simulated. Power consumption of the quantizer is given analytically. This topology is suitable to build high resolution ΔΣ modulator with low power consumption under low voltage.
  • Keywords
    comparators (circuits); delta-sigma modulation; feedforward; network topology; simulation; ΔΣ modulator; feed forward topology; multi-bit quantizer; power consumption; simulation; single-comparator;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radio-Frequency Integration Technology (RFIT), 2011 IEEE International Symposium on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4577-0517-5
  • Type

    conf

  • DOI
    10.1109/RFIT.2011.6141773
  • Filename
    6141773
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3190278