Title :
A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder
Author :
Howland, Chris ; Blanksby, Andrew
Author_Institution :
VLSI Res. Dept., Agere Syst., Holmdel, NJ, USA
Abstract :
A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW
Keywords :
error correction codes; iterative decoding; parallel architectures; 1 Gbit/s; 220 mW; coding gain; decoding algorithm; low density parity check code decoder; parallel architectures; power dissipation; switching activity; throughputs; Bipartite graph; Iterative algorithms; Iterative decoding; Message passing; Parity check codes; Power dissipation; Sparse matrices; Throughput; Turbo codes; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929780
