Title :
Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS
Author :
Ashbrook, Jonathan B. ; Shanbhag, Naresh R. ; Koetter, Ralf ; Blahut, Richard E.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
This paper presents the first integrated circuit implementation of a Hermitian decoder thereby proving its practical viability. Hermitian codes provide much larger block lengths (n=4080) compared to that of the popular Reed-Solomon (RS) codes (n=256) over the same field (GF(256)). This translates to a coding gain of 0.6 dB for the same rate. However, Hermitian codes were deemed to be too complex to implement until the emergence of a recent algorithmic breakthrough which made the complexity of Hermitian decoders comparable to that of RS codes. Based on Koetter´s decoding algorithm, the chip architecture consists of an array of sixteen interdependent Berlekamp-Massey algorithm (BMA) blocks. Thus, the same IC can be used for decoding RS codes as well. The decoder IC is designed in a 3.3 V, 0.35 μm, four-metal CMOS process and can correct up to t=60 errors per block of n=4080 words at a rate of 400 Mb/s. The IC prototype consumes 3.0 W with a 50 MHz clock
Keywords :
CMOS digital integrated circuits; Hermitian matrices; block codes; decoding; 0.35 micron; 3.0 W; 3.3 V; 400 Mbit/s; 50 MHz; CMOS; Hermitian decoder IC; Koetter´s decoding algorithm; block lengths; coding gain; four-metal CMOS process; interdependent Berlekamp-Massey algorithm blocks; Application specific integrated circuits; CMOS integrated circuits; Computational complexity; Data visualization; Decoding; Error correction; Error correction codes; Iterative algorithms; Polynomials; Rats;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929782