Current reusing low power fast settling multi-standard CMOS fractional-N frequency synthesizer

Author

Lou, Wenfeng ; Feng, Peng ; Wu, Nanjian

Author_Institution

State Key Lab. for Superlattices & Microstructures, Inst. of Semicond., Beijing, China

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

129

Lastpage

132

Abstract

A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practice application. This PLL is implemented in a 0.18μm technology. The frequency range is 0.3GHz to 2.54GHz and the settling time is less than 5us over the entire frequency range. It consumes only 4.35mA@1.8V.

Keywords

CMOS integrated circuits; frequency synthesizers; low-power electronics; phase locked loops; random-access storage; current 4.35 mA; current reusing technique; fractional-N frequency synthesizer; frequency 0.3 GHz to 2.45 GHz; frequency presetting technique; low power fast settling multi-standard CMOS; non-volatile memory; phase locked loops; repetitive calibration process; size 0.18 mum; voltage 1.8 V; Calibration; Frequency measurement; Frequency synthesizers; Nonvolatile memory; Phase locked loops; Phase noise; Synthesizers; NVM; Phase-locked loop (PLL); current reusing; divide-by-2; fast settling; forward-body bias (FBB); multi-standard;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology (RFIT), 2011 IEEE International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4577-0517-5

Type

conf

DOI

10.1109/RFIT.2011.6141780

Filename

6141780