A high performance architecture for computing burrows-wheeler transform on FPGAs

Burrows-Wheeler Transform (BWT) has applications in diverse areas such as compressed string matching, biological sequence analysis, error correction, and channel coding. Numerous efforts have been made to improve the performance of BWT in software and hardware. Its use in real time applications such as deep packet inspection and channel coding requires efficient hardware implementations that must yield high throughput. This paper presents a novel hardware technique to compute BWT on a Field Programmable Gate Array (FPGA). The technique is based on using a limited length of suffixes, a parallel suffix sorter, and an efficient First-In-First-Out (FIFO) memory pipeline to sort these suffixes. The Longest Common Prefix (LCP) known for the target application is used to determine the length of suffix. The hardware complexity analysis shows that our technique scales linearly with the length of string and the claim is verified by the hardware synthesis results. In terms of throughput (even in number of clock cycles), our technique outperforms the existing state of the art hardware techniques by over four times.