Let´s think analog

In the area of testing ICs, once an IC has failed a traditional go/no-go test, it needs to be tested further to determine if it can support error-tolerant operation for one or more high volume customers. This test must be very efficient since many chips will probably fail, and those that pass will be sold at a discount. We have already developed several efficient test procedures to support error-tolerance. One is a built-in self-test methodology that can sort chips into various bins based on their error-rate, just like resistors are sorted into 1%, 5% and 10% bins (Breuer, 2004). Digital systems designers have almost always focused on the concept of exact computational capability. Error-tolerant VLSI chips are a step in this direction using today´s technologies, addressing current computational needs, and accepting present realities of scale and yield.