DocumentCode :
3190861
Title :
An efficient application-specific instruction-set processor for packet classification
Author :
Ahmed, Omnia ; Areibi, Shawki
Author_Institution :
Sch. of Eng., Univ. of Guelph, Guelph, ON, Canada
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls and traffic billing, just to name a few. However, classification can be a bottleneck in the above mentioned applications if not implemented properly and efficiently. In this paper we propose an Application Specific Instruction Processor (ASIP) implementation for the PCIU (Packet Classification with an Incremental Update) algorithm. The proposed ASIP design is verified and tested using the ClassBench. Results obtained indicate that the ASIP implementation achieves on average 4× speed-up in terms of preprocessing and 21× speed-up in terms of classification over a state-of-the-art Xeon processor.
Keywords :
instruction sets; microprocessor chips; packet radio networks; pattern classification; ASIP design; ClassBench; PCIU algorithm; Xeon processor; application specific instruction set processor; network services; packet classification with an incremental update; Algorithm design and analysis; Benchmark testing; Clocks; Computer architecture; Engines; Hardware; Software algorithms; ASIP; Network Processors; Packet Classification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-2078-5
Type :
conf
DOI :
10.1109/ReConFig.2013.6732271
Filename :
6732271
Link To Document :
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