High-speed and low-power on-chip global link using continuous-time linear equalizer

Author

Zhang, Yulei ; Buckwalter, James F. ; Cheng, Chung-Kuan

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California at San Diego (UCSD), La Jolla, CA, USA

fYear

2010

fDate

25-27 Oct. 2010

Firstpage

5

Lastpage

8

Abstract

A new equalized on-chip global link structure is proposed for ultra-high-speed and low-energy communication by utilizing continuous-time linear equalizer (CTLE). Modeling and optimization approaches for each building block are introduced and a low-power driver-receiver co-design methodology is proposed to greatly reduce energy-per-bit by 50%. Final design can achieve 20 Gbps signaling over 10 mm, 2.2 um-pitch on-chip T-line with 11 ps/mm latency and 0.19 pJ/b energy in 45 nm CMOS.

Keywords

CMOS integrated circuits; circuit optimisation; driver circuits; integrated circuit interconnections; low-power electronics; CMOS integrated circuit; continuous-time linear equalizer; high-speed on-chip global link; low-energy communication; low-power driver-receiver co-design; low-power on-chip global link; on-chip T-line; optimization; size 45 nm; ultra-high-speed communication; Driver circuits; Integrated circuit modeling; Optimization; Receivers; Resistance; System-on-a-chip; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-6865-2

Electronic_ISBN

978-1-4244-6866-9

Type

conf

DOI

10.1109/EPEPS.2010.5642530

Filename

5642530