Title :
An empirical study of performance and power scaling of low voltage DDR3
Author :
Ji, Steven Yun ; Loop, Becky ; James, Patrick D. ; Paranjape, Vivek
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Memory power consumption has become a main driving force of new memory technologies. Low voltage DDR3 (DDR3L) has emerged to provide optimal solution for performance and power for certain market segments. With empirical data, this paper demonstrates the scaling of DDR3L signal integrity performance and power consumption at full system level. The signal integrity performance is degraded by 10~20% in terms of voltage and timing margin with strong DRAM vendor sensitivity. The DRAM power consumption is reduced by ~20%. The impact to mobile notebook average and self-refresh power is also examined.
Keywords :
DRAM chips; low-power electronics; performance evaluation; power aware computing; DDR3L signal integrity performance; DRAM power consumption; DRAM vendor sensitivity; low voltage DDR3; memory power consumption; memory technology; mobile notebook average; power scaling; self-refresh power; Batteries; Power demand; SDRAM; Silicon; Timing; Voltage measurement; DDR3; DDR3L; average power; performance scaling; self-refresh power; signal integrity; thermal design power;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
DOI :
10.1109/EPEPS.2010.5642531
