DocumentCode :
3190984
Title :
Two-phase resonant clock distribution
Author :
Chueh, Juang-Ying ; Papaefthymiou, Marios C. ; Ziesler, Conrad H.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Ann Arbor Univ., USA
fYear :
2005
fDate :
11-12 May 2005
Firstpage :
65
Lastpage :
70
Abstract :
In this paper, we present the design and evaluation of a two-phase resonant clock generation and distribution system with layout-extracted inductor parameters in a 0.13μm copper process. The design includes a programmable replenishing clock generator and tunable capacitors that enable the exploration of skew, jitter, and clock amplitude. Our simulation results show that worst-case skew is within 8.5% of clock period in the range of 790MHz to 1.22GHz under a variety of load imbalance conditions. Furthermore, energy dissipation is at least 60% lower than conventional square waveform distribution.
Keywords :
circuit simulation; clocks; logic design; logic simulation; network analysis; network topology; 0.13 micron; 0.79 to 1.22 GHz; clock amplitude exploration; energy dissipation; jitter exploration; layout-extracted inductor parameter; load imbalance; programmable replenishing clock generator; skew exploration; square waveform distribution; tunable capacitor; two-phase resonant clock distribution; two-phase resonant clock generation; Capacitors; Clocks; Energy dissipation; Frequency; Inductors; Jitter; Logic; Network topology; Resonance; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
Type :
conf
DOI :
10.1109/ISVLSI.2005.74
Filename :
1430112
Link To Document :
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