• DocumentCode
    3191004
  • Title

    Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture

  • Author

    Xu, Zheng ; Beece, Adam ; Zhang, Dingyou ; Chen, Qianwen ; Rose, Kenneth ; Lu, Jian-Qiang

  • Author_Institution
    Dept. of Electr., Rensselaer Polytech. Inst., Troy, NY, USA
  • fYear
    2010
  • fDate
    25-27 Oct. 2010
  • Firstpage
    37
  • Lastpage
    40
  • Abstract
    3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality, heterogeneous integration, power and cost. In this work, we consider the case where solder balls and through-strata-vias (TSVs) are paired to electrically connect stacked chips in a vertical fashion. For the given solder-TSV configurations, transient analysis (e.g. the 3D bathtub contour) shows a good behavior of solder-TSV signal integrity in the time domain. With regard to the frequency response from 1 MHz to 10 GHz, the performances are compared among different solder-TSV configurations. Solders with diameters of 25 - 100 μm have negligible losses in their electrical performance. The gain along the signal path is reduced with the increasing number of stacked strata and eye diagrams get distorted correspondingly. As the site offset between solders and TSVs becomes large, the signal loss is exacerbated due to the loss from the needed redistribution layer (RDL). In the solder-TSV chain structure, the electrical characteristics also deteriorate with long RDLs. Two different solder-TSV arrays give very similar near-end crosstalk (NEXT) and far-end crosstalk (FEXT). In addition, the return loss, insertion loss, NEXT and FEXT of a rhombus solder-TSV array are accurately modeled by a SPICE netlist. The circuit results show very small fitting errors for the magnitude and phase of elements in the scattering matrix. This modeling approach enables 3D architecture evaluation and design using current 2D CAD tools.
  • Keywords
    CAD; S-matrix theory; SPICE; ball grid arrays; integrated circuit interconnections; semiconductor industry; solders; 2D CAD tools; 3D bathtub contour; 3D integration; SPICE netlist; electrically connect stacked chips; far-end crosstalk; near-end crosstalk; redistribution layer; scattering matrix; semiconductor industry; signal path; solder balls; solder-TSV configurations; through-strata-vias; transient analysis; Crosstalk; Insertion loss; Integrated circuit modeling; SPICE; Solid modeling; Three dimensional displays; Through-silicon vias; 3D integration and packaging; Through-Strata-Via (TSV); electrical performance modeling; solder ball;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-6865-2
  • Electronic_ISBN
    978-1-4244-6866-9
  • Type

    conf

  • DOI
    10.1109/EPEPS.2010.5642538
  • Filename
    5642538