A modified cascaded sigma-delta modulator with improved linearity

Author

Rusu, Ana ; Ismail, Mohammed ; Tenhunen, Hannu

Author_Institution

LECS/ICT, R. Inst. of Technol. Stockholm, Sweden

fYear

2005

fDate

11-12 May 2005

Firstpage

77

Lastpage

82

Abstract

This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10MHz. The proposed modulator architecture employs the 2nd order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A data-weighted-averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18μm CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.

Keywords

CMOS integrated circuits; cascade networks; circuit simulation; delta-sigma modulation; intermodulation distortion; modulators; sigma-delta modulation; 0.18 micron; 0.18μm CMOS process; 1.8 V; 10 MHz; 4 bit; DAC; DC; SFDR; SNDR; data-weighted-averaging technique; digital-to-analog converter; feedforward signal path; frequency band; intermodulation distortion; modulator architecture; oversampling ratio; sigma-delta modulator; signal-to-noise plus distortion ratio; spurious free dynamic range; Bandwidth; CMOS technology; Chirp modulation; Delta-sigma modulation; Dynamic range; Feedback; Integrated circuit technology; Linearity; Noise shaping; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

Print_ISBN

0-7695-2365-X

Type

conf

DOI

10.1109/ISVLSI.2005.10

Filename

1430114