Title :
RC passive equalizer for through silicon via
Author :
Sun, Ruey-Bo ; Wen, Chang-Yi ; Wu, Ruey-Beei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A resistance and capacitance (RC) passive equalizer is proposed to improve the eye diagram of a through silicon via (TSV) in this paper. To begin with, an analytical circuit model of the TSV is derived by using the transmission line theory, and based on which, the simplified circuit model is obtained. It is shown that the insertion loss of the TSV from DC to several GHz mainly depends on the capacitance of the oxide film and the lossy silicon substrate. Due to this inherent property of the TSV, the proposed RC equalizer can be designed to perfectly compensate these two lossy effects. Besides, the design formula is also given. A ten-stacked TSV with a PRBS of 20 Gb/s bit rate and 20 ps rising edge is taken as an example. By the help of the RC equalizer, the output eye diagram has nearly zero timing jitter and two times improvement in eye opening.
Keywords :
capacitors; equalisers; integrated circuit interconnections; integrated circuit packaging; resistors; three-dimensional integrated circuits; timing jitter; transmission line theory; RC passive equalizer; bit rate 20 Gbit/s; circuit model; eye diagram; resistance-capacitance passive equalizer; through silicon via; timing jitter; transmission line theory; Capacitance; Equalizers; Insertion loss; Integrated circuit modeling; Silicon; Substrates; Through-silicon vias; Equalizer; through silicon via (TSV);
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
DOI :
10.1109/EPEPS.2010.5642540
