• DocumentCode
    3191050
  • Title

    Interface socket design methodology to generate embedded DRAM macros

  • Author

    Haga, Ryo ; Kaneko, Tetsuya ; Nakayama, Atsushi ; Miyano, Shinji ; Takenaka, Hiroyuki ; Numata, Kenji ; Koinuma, Hiroyuki ; Hojo, Takehiko ; Sato, Akikuni ; Kouchi, Toshiyuki ; Mimoto, Kenichiro ; Tazawa, Masaaki ; Ohkubo, Tsutomu ; Andou, Takanori ; Aman

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    537
  • Lastpage
    540
  • Abstract
    A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 μm technology
  • Keywords
    DRAM chips; integrated circuit design; reconfigurable architectures; 0.18 micron; 12 Mbit; common DRAM core; embedded DRAM macros; interface socket design methodology; reconfigurability; synchronous interface socket; Decoding; Design engineering; Design methodology; Information systems; Microelectronics; Power generation; Random access memory; SDRAM; Sockets; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits, 2001, IEEE Conference on.
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-6591-7
  • Type

    conf

  • DOI
    10.1109/CICC.2001.929837
  • Filename
    929837
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3191050