A study of reduced-terminal models for system-level SSO noise analysis

SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.