DocumentCode :
3191086
Title :
A core frequency-loss estimation methodology for a power-delivery network with reduced decoupling capacitance
Author :
Srinivasan, Krishna ; Quddus, Ruhul ; Mortensen, Russell K. ; Chen, Herh Nan ; Shamanna, Manjunath ; Chin, Po-loong Paul
Author_Institution :
Intel Corp., Chandler, AZ, USA
fYear :
2010
fDate :
25-27 Oct. 2010
Firstpage :
53
Lastpage :
56
Abstract :
This paper proposes a simulation methodology to quantify the relative impact to the maximum CPU core operating frequency, also known as Fmax, for different power-delivery network designs. Good measurement-simulation correlation for designs with different decoupling capacitance has been presented to validate the proposed technique. Through careful consideration of the process, voltage, and temperature in the simulation, together with the availability of more accurate simulation tools to characterize the power-delivery network, good agreement with measurement data has been obtained.
Keywords :
low-power electronics; microprocessor chips; core frequency-loss estimation methodology; maximum CPU core operating frequency; measurement-simulation correlation; power-delivery network design; reduced decoupling capacitance; simulation methodology; Clocks; Delay; Frequency measurement; Inverters; Noise; Noise measurement; Temperature measurement; Core Frequency; Fmax; Power-delivery Network;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
Type :
conf
DOI :
10.1109/EPEPS.2010.5642542
Filename :
5642542
Link To Document :
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