Title :
Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology
Abstract :
3D integration offers inter-strata interconnect with high connectivity density, low parasitics, and shorter lengths. This bring advantages in increased interconnect bandwidth, reduced interconnect latency and reduced power consumption in comparison with individual packaged chips on a board or packages with wire bonded stacked die. 3D integration can compete with, or even surpass, SoC (system on a chip) integration in terms of interconnect performance while allowing for differentiated process technologies for the various strata.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit packaging; 3D integration technology; high connectivity density; individual packaged chips; inter-strata interconnect; interconnect bandwidth; interconnect latency; process technology development; system on a chip integration; wire bonded stacked die;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479686
