Abstract :
Summary form only given. Although more and more engineering resources are being focused on verification, most of the effort is expended on re-simulating what has already been simulated. And once the effort is through, only 20% of the state space has been verified, at best. Verification today is a frustrating, open-loop process that often doesn´t end even after the integrated circuit ships. In response, the whole verification methodology infrastructure is undergoing major changes - from adoption of assertion-based verification, coverage-driven verification, to new approaches in test bench generation/optimization, integrated hardware acceleration and more. In this session, Robert Hum will explore these and other new solutions and innovations in functional verification technology,and discuss the impact of these changes on the EDA industry.
Keywords :
circuit simulation; electronic design automation; integrated circuit testing; EDA industry; assertion-based verification; coverage-driven verification; electronic design automation; endless verification loop; integrated circuit; integrated hardware acceleration; open-loop process; state space; test bench generation; test bench optimization; verification methodology infrastructure; Circuit simulation; Circuit testing; Electronic design automation and methodology; Hardware; Life estimation; Marine vehicles; Optimization methods; Speech; State-space methods; Technological innovation;
