VLSI arrays for speech processing with linear predictive coding

The covariance analysis of linear predictive coding has wide applications, especially in speech recognition and speech signal processing. Real-time applications demand very high processing speed for linear predictive coding analysis. VLSI technology which possesses properties of low-cost, high-speed and massive computing capabilities is a suitable candidate. In this paper, systolic array processors for the covariance analysis of linear predictive coding are developed. The covariance analysis of linear predictive coding contains a large set of irregular and nested recurrence equations. Systolizing the algorithm is a difficult task for such a complex problem, Existing methods of systematic design for systolic arrays are not much helpful to this problem. To overcome it, a break-combination method is presented in this paper. In this manner, the task is first decomposed and then mapped onto several interconnected systolic arrays. The resulting systolic arrays of the sub problems are then combined to form a complete solution