DocumentCode :
3191362
Title :
High speed max-log-MAP turbo SISO decoder implementation using branch metric normalization
Author :
Han, J.H. ; Erdogan, A.T. ; Arslan, T.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ., UK
fYear :
2005
fDate :
11-12 May 2005
Firstpage :
173
Lastpage :
178
Abstract :
The authors present a turbo soft-in soft-out (SISO) decoder based on max-log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique based on branch metric normalization is introduced to improve the speed performance of the decoder. The turbo decoder with the proposed technique has been synthesized to evaluate its power consumption and area usage using a 0.18um standard CMOS cell library. It is shown that while power consumption and area usage change slightly with our technique, it achieves up to 58% speed-up compared to a conventional SISO decoder architecture.
Keywords :
CMOS integrated circuits; circuit simulation; decoding; digital signal processing chips; high-speed integrated circuits; turbo codes; 0.18 micron; CMOS cell library; ML-MAP; SISO decoder architecture; branch metric normalization; max-log maximum a posteriori; max-log-MAP; power consumption; sliding window; turbo SISO decoder; turbo soft-in soft-out decoder; Bit error rate; Communication standards; Energy consumption; Hardware; Iterative decoding; Libraries; Turbo codes; Very large scale integration; Viterbi algorithm; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
Type :
conf
DOI :
10.1109/ISVLSI.2005.37
Filename :
1430129
Link To Document :
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