Title :
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
Author :
Cardoso, T.M.G. ; Rosa, L.S. ; Marques, F.S. ; Ribas, R.P. ; Reis, A.I.
Author_Institution :
Inst. de Inf. - UFRGS, Porto Alegre
Abstract :
This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.
Keywords :
application specific integrated circuits; binary decision diagrams; field programmable gate arrays; integrated circuit design; logic design; transistor circuits; ASIC; FPGA; four-input networks; logic styles; transistor network synthesis; transistor reordering; transistor topology; Boolean functions; Circuit topology; Costs; Data structures; Delay; Field programmable gate arrays; Logic circuits; Network synthesis; Network topology; Table lookup; BDDs; Logical effort; Transistor networks; logic synthesis;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479696
