Implementation of an Asynchronous FFT Processor

As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. The alternative approach is called a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent frequency scaling can be performed by minimizing inter-domain synchronization costs. The CMOS processor the power consumption is directly proportional to the frequency of operation. The design is divided into various zones and operating with different frequencies thereby reducing the power consumption. This paper proposes GALS (Globally Asynchronous Locally Synchronous) based FFT processor.