Quality of a Bit (QoB): A New Concept in Dependable SRAM

Author

Fujiwara, Hidehiro ; Okumura, Shunsuke ; Iguchi, Yusuke ; Noguchi, Hiroki ; Morita, Yasuhiro ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

Author_Institution

Kobe Univ., Kobe

fYear

2008

fDate

17-19 March 2008

Firstpage

98

Lastpage

102

Abstract

We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. By carrying out Monte Carlo simulation of dynamic cell stability in a 90- nm process technology, we confirmed the advantage of the proposed SRAM.

Keywords

Monte Carlo methods; SRAM chips; 90 nm process technology; Monte Carlo simulation; dependable SRAM; dynamic cell stability; high speed mode; memory cells; quality of a bit; size 90 nm; Application software; Bit error rate; Cryptography; Manufacturing; Negative bias temperature instability; Niobium compounds; Random access memory; Silicon; Stability; Titanium compounds; Quality of a bit; SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

978-0-7695-3117-5

Type

conf

DOI

10.1109/ISQED.2008.4479706

Filename

4479706