Optimization of thermal via design parameters based on an analytical thermal resistance model

In dealing with thermal via design, this paper presents a simple analytical model that provides an efficient approach for analysis of thermal via pads. Small vias close to one another form a cluster with a relatively large dimension. Heat flow across the substrate thickness in the via cluster is much more significant than the heat spreading effect in the lateral direction. Therefore, predominantly one-dimensional heat conduction allows analytical simplification by modeling the thermal via as parallel networks. Through single and multiple via modeling, an analytical relationship of thermal resistance versus the via design parameters is found and presented in dimensionless form. The via design parameters include hole diameter, pitch, plating thickness, and the void level of the filled materials inside the vias. Optimization of the design parameters is obtained using thermal resistance as the objective function. The analytical results were correlated with an FEA model and can be used as thermal via design guidelines in electronics packaging