Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator

In this paper, we discuss user space parameters and performance modeling of 3-D stencil computing on a stream-based FPGA accelerator. We use a heat conduction simulation as a benchmark and evaluate a performance for that developed with MaxCompiler, a kind of high-level synthesis tools for FPGAs, and MaxGenFD, a domain specific framework on the MaxCompiler for finite-difference equations. Performance comparison with multi-threaded and SIMD-enabled CPU implementation shows FPGA design achieved about six times speedup when a user chose the best architectural parameters. Energy consumptions of the FPGA accelerator were measured and it is shown that the best configuration in terms of performance also shows the lowest energy consumption.