• DocumentCode
    3191680
  • Title

    Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication framework

  • Author

    Thomas, Kevin L. ; Thompson, Michael

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Bucknell Univ., Lewisburg, PA, USA
  • fYear
    2013
  • fDate
    9-11 Dec. 2013
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    In this paper we present a model for predicting performance of a distributed, reconfigurable computing cluster using commodity parts, specifically the Digilent OpenSPARC development board, and the SIRC Framework, developed by Microsoft Research. The goal of this work is to assist in determining the feasibility of deploying a similar system for a given problem. This work is aimed a low-budget and introductory projects that wish to leverage commodity hardware. This paper also provides experimental results for a reconfigurable, distributed system simulating various loading configurations.
  • Keywords
    distributed processing; field programmable gate arrays; performance evaluation; reconfigurable architectures; Digilent OpenSPARC development board; Microsoft Research; OpenSPARC FPGA board; SIRC communication framework; commodity hardware; distributed reconfigurable computing cluster performance prediction; loading configurations; performance modeling; simple interface for reconfigurable computing; Computational modeling; Cryptography; Delays; Field programmable gate arrays; Hardware; Mathematical model; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-2078-5
  • Type

    conf

  • DOI
    10.1109/ReConFig.2013.6732319
  • Filename
    6732319