Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA

Field Programmable Gate Arrays are an attractive platform for reconfigurable computing due to their inherent flexibility and low entry cost relative to custom integrated circuits. With modern programmable devices exploiting the most recent fabrication nodes, designs are able to achieve device-level performance and power efficiency that rivals custom integrated circuits. This paper presents the benchmarking of performance and power efficiency of a variety of standard benchmarks on a Xilinx Virtex-6 75k device using a tiled, partially reconfigurable architecture. The tiled architecture provides the ability to swap in arbitrary processing units in real-time without re-synthesizing the entire design. This has performance advantages by allowing multiple processors and/or hardware accelerators to be brought online as the application requires. This also has power efficiency advantages by keeping unused tiles un-programmed to reduce static power consumption. This paper presents the benchmarking results using a custom Virtex-6 board with a power regulation system that allows instrumentation of each power supply on the Virtex-6 to measure both performance and power efficiency simultaneously.