DocumentCode
3191729
Title
Evaluating the data integrity of memory systems by configurable Markov models
Author
Ottavi, M. ; Schiano, L. ; Lombardi, F. ; Pontarelli, S. ; Cardarilli, G.C.
Author_Institution
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, CA, USA
fYear
2005
fDate
11-12 May 2005
Firstpage
257
Lastpage
259
Abstract
In this paper, a novel method for the evaluation of the bit error rate (BER) as measure for assessing data integrity in memory systems is proposed; such method improves modeling by introducing configurability features in the Markov chains to account for environmental and operational changes. For modeling erasures and random errors, the occurrence of new time-varying features is introduced in the analysis to characterize the behavior of memory systems for space applications (using Reed-Solomon codes as EDAC). Moreover, differently from existing techniques, the nature of these features (such as scrubbing and the effects of the so-called South Atlantic Anomaly on SEU rates) is assessed using a deterministic framework.
Keywords
Markov processes; VLSI; circuit reliability; data integrity; error statistics; logic testing; memory architecture; EDAC; Reed-Solomon code; SEU rate; South Atlantic anomaly; bit error rate; configurable Markov models; data integrity measure; erasure modelling; memory system; random error modelling; Aerospace electronics; Bit error rate; Data engineering; Error correction codes; Instruments; Reed-Solomon codes; Satellites; Single event upset; Time varying systems; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.30
Filename
1430145
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