DocumentCode
3191733
Title
Synthesis of self-resetting stage logic pipelines
Author
Alsharqawi, Abdelhalim ; Ejnioui, Abdel
Author_Institution
Dept. of Electr. & Comput. Eng., Central Florida Univ., USA
fYear
2005
fDate
11-12 May 2005
Firstpage
260
Lastpage
262
Abstract
In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented and tested on a set of benchmark circuits. Also, fast heuristics are being developed to synthesize large gate netlists into SRSL pipelines.
Keywords
integer programming; integrated circuit testing; logic design; logic gates; network synthesis; benchmark circuit; integer programming; large gate netlist synthesis; self-resetting stage logic pipeline; Circuit synthesis; Clocks; Costs; Delay; Design methodology; Gravity; Logic; Network synthesis; Pipeline processing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.70
Filename
1430146
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