Configurable multiprocessors for high-performance MPEG-4 video coding

Author

Chouliaras, V.A.

Author_Institution

Loughborough Univ., UK

fYear

2005

fDate

11-12 May 2005

Firstpage

272

Lastpage

273

Abstract

We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder.

Keywords

digital signal processing chips; multi-threading; parallel processing; reconfigurable architectures; reduced instruction set computing; system buses; system-on-chip; video coding; MPEG-4 video coding; bus-based SoC multiprocessor; configurable multiprocessors; dynamic instruction count; hardware-based multiprocessing primitives; multithreaded MPEG-4 video encoder; open-source 32-bit RISC CPU; threaded video encoder; Ambient intelligence; Computational modeling; Jacobian matrices; MPEG 4 Standard; Parallel processing; Phase change random access memory; Very large scale integration; Video coding; Video sequences; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

Print_ISBN

0-7695-2365-X

Type

conf

DOI

10.1109/ISVLSI.2005.24

Filename

1430151