Title :
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
Author :
Mohanty, Saraju P.
Author_Institution :
Univ. of North Texas, Denton
Abstract :
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). The proposed algorithm is tested for several circuits for 45nm CMOS technology node. The experiments show that average gate leakage reduction are 67.7 % and 80.8 % for SiO2- SiON and SiO2-Si3N4, respectively.
Keywords :
CMOS integrated circuits; integer programming; DKCMOS library; ILP; RTL synthesis; gate leakage optimization; integer linear programming; leakage delay product; register-transfer level; CMOS technology; Circuit synthesis; Delay; Design optimization; Gate leakage; High K dielectric materials; High-K gate dielectrics; Libraries; Logic devices; Tunneling;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479721
