Title :
Wire length distribution model considering core utilization for system on chip
Author :
Kyogoku, Takanori ; Inoue, Junpei ; Nakashima, Hidenari ; Uezono, Takumi ; Okada, Kenichi ; Masu, Kazuya
Author_Institution :
Precision & Intelligence Lab., Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.
Keywords :
circuit optimisation; integrated circuit interconnections; large scale integration; network synthesis; system-on-chip; chip interconnects; chip size; circuit optimisation; layout-area allocation; maximum clock frequency; power consumption prediction; system LSI; system-on-chip; wire length distribution model; CMOS technology; Circuit simulation; Delay effects; Equations; Frequency; Integrated circuit interconnections; Laboratories; Power system modeling; System-on-a-chip; Wire; SoC; Wire Length Distribution; core utilization; layout-area allocation;
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
DOI :
10.1109/ISVLSI.2005.76
